This invention relates generally to a device and method for electronic data communication and particularly that between a memory controller and an array of memory chips.
Conventional memory system design uses a large number of parallel signals for the addressing, data transfer, and control of system operations. This is a very convenient means of configuring memory systems and results in very fast system operation. This is particularly true for integrated circuit, random access memory devices.
A disadvantage arises from this approach in that a large number of signal lines needs to be routed to each and every memory device in the memory system. This entails rather inefficient use of printed circuit board area and large cables and backplanes. Also, the system power supply must have higher capacity in order to deliver higher peak power for parallel signalling. In most cases, however, this inefficiency must be tolerated in order to achieve best possible speed of operation.
In some applications, on the other hand, it is possible to employ a serial link between two systems in order to reduce the number of cables therebetween, as well as the size of the cables, backplanes, and circuit boards in the systems. Overall, physical density can be dramatically improved over conventional methods, in that circuit boards can be made smaller and the total physical volume required for the connecting systems can be reduced. However, serial connections are usually slower than their parallel counterparts.
It is desirable to have simple connections between a memory controller and an array of memory devices, without compromising performance.
Accordingly, it is an object of the present invention to simplify the connections between two systems with minimum compromise on performance.
It is another object of the present invention to simplify the connections between a controller and an array of solid-state memory devices.
It is another object of the invention to provide means and method for improvements in selecting one or more memory devices within the a memory array for communication.
It is also an object of the invention to provide means and method for de-selecting the improvements in deselecting memory devices which have previously been selected for communication.
It is yet another object of the present invention to allow the memory devices of the memory array to be configured so that they are all enabled for simultaneous communication.
It is yet another object of the present invention to improve the speed of the memory devices.
These and additional objects are accomplished by improvements in the architecture of a system comprising a memory controller and an array of solidstate memory devices, and the circuits and techniques therein.
According to one aspect of the invention, an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with minimum lines. This forms an integratedcircuit memory system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized and multiplexed before being transferred between the controller module and the memory subsystem. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. When the control signal is asserted, a circuit on each memory device of the subsystem interprets the serialized bits of information as a pointer code. After the control signal is de-asserted, deasserted, the each device routes subsequent bits of the serialized information to the appropriate command, address or data registers according to the type of information pointed to by the code.
The present invention uses a serial link to interconnect between the solid-state memory devices and the controller module. The serial link greatly reduces the number of interconnections and the number of external pads for each device, thereby reducing cost. Also expansion of the memory capacity of the system is simply achieved by a higher packing density of devices on standard printed circuit boards. It is not necessary to have a variety of circuit boards for each density, since the number of address and chip select signals does not change with capacity.
An important aspect of the invention is to employ a broadcast select scheme to select or enable a given memory device chip among an array of chips in a memory board or memory module. Each memory device chip has a multi-bit set of pinouts that is connected internally to a device select circuit and externally to a multi-bit mount on the memory module""s backplane. Each multi-bit mount on the backplane is preconfigured pre-configured or keyed to a given address (represented by a multi-bit combination of xe2x80x9c0xe2x80x9ds and xe2x80x9c1xe2x80x9ds) according to its location in the array. In one embodiment, the terminals in the multi-bit mount corresponding to the xe2x80x9c0xe2x80x9d bit are set to ground potential. When a memory chip is powered on, the address of the array as defined by the mount key is passed onto the device select circuit of the chip. To select a given memory chip, the correct array address for that chip is sent to all the chips in the array via the interconnecting serial bus. This address is compared at each chip with that it acquired from its each chips mount, and the chip that matched is selected or enabled by its device select circuit. A memory chip remains selected until explicitly deselected, allowing more than one memory chip to be enabled at a time.
The invention provides a simple scheme for assigning an array address to each of the chips mounted on a memory module""s backplane. By providing the keying at the backplane instead of at the memory chips, the memory chips can be made generic. This also avoids the need for conventional use of using conventional individual chip select to enable each memory chip. This results in very low pin count in multi-chip modules, especially that of socketed modules, enabling high density package packing of memory chips on memory modules.
According to another aspect of the invention, the array of memory chips may be distributed over a plurality of memory modules. Each of the memory modules can be enabled by a module select signal from the controller module.
According to another aspect of the invention, each memory module may be further partitioned into a plurality of memory submodules. These submodules may be mounted on a memory module""s backplane and are all enabled by the same module select signal. The multi-bit address in the multi-bit mount for each memory device is partitioned into two subsets. The permutations of one subset are used to provide the different memory-device addresses on a memory submodule. The permutations of the other subset are used to provide the different memory-submodule addresses on a memory module. Thus, there is a pre-configured preconfigured multi-bit mount for each memory submodule on the memory module""s backplane.
According to another aspect of the invention, one particular key among the permutations of the multibit mounts is reserved as a xe2x80x9cmaster keyxe2x80x9d to unconditionally have each device select circuit enable its chip. In the preferred embodiment, this xe2x80x9cmaster keyxe2x80x9d is given by having all the bits of a multi-bit mount not grounded. This allows a group of chips with this xe2x80x9cmaster keyxe2x80x9d mount to be selected together.
According to yet another aspect of the invention, the broadcast select scheme has a reserved code that can be communicated to the array of memory chips on the backplane in order to deselect all previously selected chips. In the preferred embodiment, a select sequence of shifting in a pattern of all ones results in a global deselect.
Another important aspect of the invention is to implement a streaming read scheme to improve the read access of the memory system. While a chunk (e.g. 64 bits) of data is being read from the memory cells, serialized and shifted out of a memory chip, the address for the next chunk is being setup and sent to the memory chip to begin accessing the next chunk of data. The overlapping operations of reading out of one chunk of data and staging for the access of the next chunk of data greatly improve the read access speed of the memory system.
As mentioned before, the use of a serial link is unconventional for integrated circuit memory chips. These memory devices are typically random-access memories which are designed for high speed access and therefore employ parallel address and data buses. Serializing the command, address and data information for these devices is unconventional since it may require more circuitry than conventional parallel access, and may result in slower access. However, the present invention, when used in a block transfer regime (e.g., reading 4096 consecutive user bits at a time, is relatively insensitive to access time, the speed being determined largely by the data throughput once reading has begun. The present invention recognizes that employment of a serial link in the present EEPROM electrically erasable programmable read only memory (xe2x80x9cEEPROMxe2x80x9d)system architecture, particularly with the features of broadcast selection and streaming read, results in simplified connections therein without compromising access speed for the intended application.